Delay Locked Loop

ABSTRACT

A delay locked loop, comprises: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.

CROSS REFERENCE

This application claims priority from a provisional patent application entitled “Apparatuses, Methods, and Systems Using Integrated Circuits” filed on Apr. 19, 2013 and having an Application No. 61/814,153. Said application is incorporated herein by reference.

FIELD OF INVENTION

This invention generally relates to a delay locked loop, and, in particular, to a low power delay locked loop for semiconductor devices, including memory devices.

BACKGROUND

In a high speed synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (“DDR SDRAM”), data is transferred (input from or output to) to other devices in synchronization with an external clock signal. The high speed synchronous semiconductor memory device such as the DDR SDRAM performs an input or output operation in synchronization with not only a rising edge but also a falling edge of the external clock signal. Typically, in a system or a circuit including a semiconductor memory, a clock signal is used as a reference clock signal for adjusting operation timing to guarantee stable data access and data transfer without error. For stable data access and data transfer, a delay occurring from processing and receiving the data should be compensated for during the data transfer by exactly setting the data transfer at edges of the clock signal or at centers of the clock signal.

To control the data transfer timing, the clock signal needs to be synchronized with the transition timing of the external clock. Synchronous semiconductor memory devices include a clock synchronization circuit for this purpose. The clock synchronization circuit may include a phase locked loop (“PLL”) and/or a delay locked loop (“DLL”). Typically, in case that a frequency of the external clock differs from that of an internal clock in the semiconductor memory device, the PLL is used because the clock synchronization circuit can adjust the frequency of an internal clock in the semiconductor memory device. In case that a frequency of the external clock is the same as that of an internal clock in the semiconductor memory device, the DLL is generally used to adjust the phase of the internal clock.

The delay locked loop generates internal clock signals based on the reference clock by compensating for clock skew occurring in the data path. The data path has a predetermined delay amount estimated from the clock skew, where the data or the clock signal passes through the semiconductor memory device. The generated internal clock signals can then be used for synchronizing data input/output.

Although a delay locked loop works well to generate the internal clock signals for the semiconductor memory device, the DLL of the current art consume large amounts of power which are not suitable for low-power devices. For instance, a regulator is generally required in the DLL of the current art to supply a stable current to the various elements in the DLL circuit. The regulator consumes a large amount of power, and is not suited for low power applications. In additional, external biasing is necessary for the DLL of the current art to operate correctly, which is another source of power consumption. Therefore, it is desirable to provide new methods and circuits for a low power DLL, and, in particular to, a DLL that has self-biased elements and that does not need a regulator for supplying currents to the elements of the DLL circuit.

SUMMARY OF INVENTION

An object of this invention is to provide a low power delay locked loop.

Another object of this invention is to provide a self-biased delay locked loop.

Yet another object of this invention is to provide a bandwidth programmable delay locked loop.

Briefly, the present invention discloses a delay locked loop, comprising: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.

An advantage of this invention is that a low power delay locked loop is provided.

Another advantage of this invention is that a self-biased delay locked loop is provided.

Yet another advantage of this invention is that a bandwidth programmable delay locked loop is provided.

DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, aspects, and advantages of the invention can be better understood from the following detailed description of the preferred embodiment of the invention when taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a block diagram for a delay locked loop (“DLL”) of the present invention.

FIG. 2 illustrates a circuit diagram for a charge pump of a DLL of the present invention.

FIG. 3 illustrates a circuit diagram for a bias generation circuit of a DLL of the present invention.

FIG. 4 illustrates a circuit diagram for an operational transconductance amplifier of a charge pump of the present invention.

FIG. 5 illustrates a circuit diagram for another operational transconductance amplifier of a charge pump of the present invention.

FIG. 6 illustrates a slave bias circuit of a DLL of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following detailed description of the embodiments, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration of specific embodiments in which the present invention may be practiced.

Generally, a memory system, e.g., DDR SDRAM, requires a clock signal with very fine steps to control the delay precisely for N-bit wide data with the clock positioned at the center. To generate the clock signal for the memory system, a delay locked loop (“DLL”) of the present invention is used to synchronize one or more internal clock signals to a reference clock for the incoming data signal. The internal clock signals must be very precise clock signals relative to the incoming data, which are routed to all the parallel (N-bit) data paths macros.

FIG. 1 illustrates a block diagram for a delay locked loop of the present invention. A DLL system of the present invention comprises a bias generation circuit 8, an initialization circuit 10, a loop capacitor 12, a charge pump 14, a phase detector 16, and a delay chain 20. The DLL system works in a negative feedback loop to match the phase of a differential reference clock signal L_(in). The delay chain 20 outputs a feedback clock signal L_(out), a differential signal, to the phase detector 16. The phase detector 16 compares the feedback clock signal L_(out) with the reference clock signal L_(in). The reference clock signal L_(in) can be received from a phase locked loop (“PLL”) of the associated memory system (or from another part of the semiconductor device). The phase detector 16 outputs signals up, up, dn, and dn which are indicative of the relative phase differences of the differential signals L_(in) and L_(out).

The outputs signals up, up, dn, and dn are inputted to the charge pump 14 to generate a charge pump voltage V_(CP). The charge pump voltage V_(CP) is connected to the initialization circuit 10, the loop capacitor 12, and the bias generation circuit 8. During initiation of the DLL, the initialization circuit 10 provides a pulse generation voltage to the voltage V_(CP). After initiation, the negative feedback loop of the DLL takes over, and the initiation circuit 10 is deactivated.

When there is a phase difference between the reference clock signal L_(in) and the feedback clock signal L_(out), the output signals up,up, dn, and dn of the phase detector 16 indicate such changes, which are then used to adjust the feedback clock signal L_(out) to match the phase of the reference clock signal L_(in). For instance, when the output signals up and dn are equal, then the positive signal of the reference clock signal L_(in) and the positive signal of the feedback clock signal L_(out) are in phase. When the reference clock signal L_(out) is leading the feedback clock signal L_(in) in phase, then a continuous output signal do can be generated. This in turn will decrease the control voltages for the delay chain 20 to adjust the phase of the feedback clock signal L_(out) to closer match the reference clock signal L_(in). When the feedback clock signal L_(out) is lagging the reference clock signal L_(in), then a continuous output signal up can be generated, which increases the control voltages for the delay chain 20 to adjust the phase of the feedback clock signal L_(out) to closer match the reference clock signal L_(in). Likewise, the output signals up and dn can be generated accordingly to adjust the negative signals of the reference clock signal L_(in) and the feedback clock signal L_(out).

The charge pump voltage V_(CP) is inputted to the bias generation circuit 8 to generate biasing voltages, e.g., V_(bias master p), V_(bias master n) and any slave biases as needed. The biasing voltages are inputted to the delay chain 20 for controlling the phase delay for internal clocks signals that are generated by the delay chain 20, e.g., the internal clock signals Φ₀, Φ₁, Φ₂, and Φ₃. Typically, the internal clock signals are a preset number of degrees out of phase with the reference clock signal L_(in). For instance, the internal clock signal Φ₀ can be 90 degrees out of phase with the reference clock signal L_(in); the internal clock signal Φ₁ can be 180 degrees out of phase with the reference clock signal L_(in); the internal clock signal Φ₂ can be 270 degrees out of phase with the reference clock signal L_(in); and the internal clock signal Φ₃ can be 360 degrees out of phase with the reference clock signal L_(in).

Bandwidth control can adjust the internal clock signals to quickly adapt to any changes in phase of the reference clock signal L_(in) by way of the negative feedback loop system of the DLL of the present invention. The DLL loop parameters like bandwidth and damping factors are programmable. For instance, the bandwidth and damping factor are a function of the charge pump, loop capacitor C1, and delay cell gain. Thus, the charge pump current and the delay cell gain can be controlled using digital control bits to program the bandwidth and the damping factor.

During steady state operation, the feedback clock signal L_(out) is substantially in phase with the reference clock signal L_(in). There might be some delay between the feedback clock signal L_(out) and the reference clock signal L_(in) due to the feedback loop routing. The delay chain 20 comprises storage delay cells, e.g., delay cells 22-30, where the delay cells are connected in series and generate the internal clock signals having a preset delay in phase. The internal clock signals can be routed to any of the parallel data paths of the memory system. Typically, the memory system may have 76 data buses of parallel inputs coming in at different frequencies and/or phases. Thus, the delay chain can be further replicated for each of the 76 data buses via a slave bias circuit (not shown).

FIG. 2 illustrates a circuit diagram for a charge pump of a DLL of the present invention. The charge pump 14 of the present invention comprises a self-biased operational transconductance amplifier (“OTA1”) 40, another self-biased operational transconductance amplifier (“OTA2”) 42, switches 60 and 70, and transistors 44-58 and 64-68 (e.g., metal-oxide-semiconductor field-effect transistors). The OTA1 40 has a positive input that is connected to the charge pump voltage V_(CP), a negative input that is connected to a voltage V_(CP) _(—) _(dummy), and differential output signals V_(BP) and V_(BN). The output signal VBP is connected to the gates of the transistors 44 and 52, and connected to the gate of the transistor 62 via the switch 60. The output signal V_(BN) is connected to the gates of the transistors 50 and 58, and connected to the gate of the transistor 68 via the switch 70. The OTA1 40 and the transistors 44-50 act as a load, which can be active to prevent spikes in the charge pump voltage V_(CP).

The transistors 44-50 are connected in series across voltages V_(DD) and V_(SS). The voltages V_(DD) and V_(SS) are the respective power and ground supplies to the respective circuit. Typically, the power supply can vary from 1.1V to 0.7V. The source of the transistor 44 is connected to the voltage V_(DD). The source of the transistor 50 is connected to the voltage V_(SS). The gate of the transistor 46 is connected to the voltage V_(SS), and the gate of the transistor 48 is connected to the voltage V_(DD). Also, the drains of the transistors 46 and 48 are connected together to generate the voltage V_(CP) _(—) _(dummy), which is inputted to the negative input of the OTA1 40.

The drains of the transistors 54 and 56 are connected to each other, providing a voltage V_(CP). The voltage V_(CPD) is applied to the positive input of the OTA2 42. The drains of the transistors 64 and 66 are connected to each other, and further connected to the output and the negative input of the OTA2 42 in a negative feedback loop. The output of the OTA2 42 is connected with the charge pump voltage V_(CP). The sources of the transistors 54 and 64 are connected together, and further connected to the drains of the transistors 52 and 62. The sources of the transistors 52 and 62 are connected to the voltage V_(DD). The sources of the transistors 56 and 66 are connected together, and further connected to the drains of the transistors 58 and 68. The sources of the transistors 58 and 68 are connected to the voltage V_(SS).

The output signal up is connected to the gate of the transistor 54. The output signal up is connected to the gate of the transistor 64. The output signal dn is connected to the gate of the transistor 56. The output signal dn is connected to the gate of the transistor 66.

The switches 60 and 70 provide a bandwidth control for the DLL negative feedback loop. The switches 60 and 70 can be programmed accordingly to adjust the bandwidth control. Generally, the switches 60 and 70 are activated, i.e., turned on, when the reference clock signal L_(in) is 1 GHz or above, otherwise the switches 60 and 70 are deactivated, i.e., turned off.

FIG. 3 illustrates a circuit diagram for a bias generation circuit of a DLL of the present invention. The bias generation circuit 8 comprises transistors 80-106 for generating the biasing voltages V_(bias master p), V_(bias master n), and V_(bias slave n). The sources of the transistors 80, 84, 88, 94, 98, and 104 are connected to the voltage V_(DD). The gates of the transistors 80 and 84 and the drain of the transistor 84 are connected together. The gates of the transistors 88, 94, 98, and 104 and the drain of the transistor 88 are connected together to generate the biasing voltage V_(bias master p). Thus, the biasing voltages can be generated from the charge pump voltage.

The drain of the transistor 88 is further connected with the drain of the transistor 86. The gate of transistor 86 is connected to the charge pump voltage V_(CP). The source of the transistor 86 is connected to the voltage VSS and the source of the transistor 90. The drain of the transistor 90 is connected with the drain of the transistor 84. The gate of transistor 90 is connected to the drains of the transistors 92 and 94 to generate a voltage V_(DSΦ). The voltage V_(DSΦ) is applied to any slave bias circuits (see FIG. 6) to generate a current locally for any other DLLs.

The sources of the transistors 82, 86, 90, 92, 96, 100, 102, and 106 are connected to the voltage V_(SS). The gate and drain of the transistor 82 and the drain of transistor 80 are connected together. The gates of the transistors 82, 92, 96 and 102 are connected together. The drain of the transistor 96 and the gate of the transistor 100 are connected together and generate the biasing voltage V_(bias master n). The drain of the transistor 100 is connected with the drain of the transistor 98. The drain of the transistor 102, the gate and the drain of the transistor 106, and the drain of the transistor 104 are connected together, and generate the biasing voltage V_(bias slave n).

FIG. 4 illustrates a circuit diagram for a self-biased operational transconductance amplifier of a charge pump of the present invention. The OTA1 40 comprises transistors 140-158. The sources of the transistors 140, 144, 148, and 152 are connected to the voltage V_(DD). The gate of the transistor 140, the gate and the drain of the transistor 144, and the drain of the transistor 150 are connected together. The gate and drain of the transistor 148, the gate of the transistor 152, and the drain of the transistor 146 are connected together, and generate the OTA1 40's output voltage V_(BP). The charge pump voltage VCP is applied to the gate of the transistor 146. The voltage V_(CP) _(—) _(dummy) is applied to the gate of the transistor 150 and to the drains of the transistors 154 and 156. The voltage V_(SS) is applied to the gate of the transistor 154, and the voltage V_(DD) is applied to the gate of the transistor 156.

The drain and gate of the transistor 142, the drain of the transistor 140, and the gate of the transistor 158 are connected to together, and generate the OTA1 40's output voltage V_(BN). The voltage V_(SS) is applied to the sources for the transistors 142, 146, 150, and 158. The drain of the transistor 152 is connected with the source of the transistor 154. The source of the transistor 156 is connected to the drain of the transistor 158. The drains of the transistors 154 and 156 are connected together.

The OTA1 40 is a self-biased operational amplifier that uses a charge pump dummy path to replicate the charge pump loading effect. The voltages V_(BP) and V_(BN) can be used to control the biasing points for the delay cells 22-30. Since OTA1 40 is self-biased, there is no need for a current source for this operational amplifier, which greatly reduces the power consumption of the DLL of the present invention.

FIG. 5 illustrates a circuit diagram for another self-biased operational transconductance amplifier of a charge pump of the present invention. The OTA2 42 comprises transistors 180-194 for generating a voltage V_(CPD) based on the charge pump voltage V_(CP). The voltage V_(DD) is applied to the sources of the transistors 180, 184, 188, and 192. The drain of the transistor 180, the gate and the drain of the transistor 182, and the gate of the transistor 194 are connected together. The gate of the transistor 180, the drain and the gate of the transistor 184, and the drain of the transistor 186 are connected together. The gate of the transistor 192, the drain and the gate of the transistor 188, and the drain of the transistor 190 are connected together. The voltage V_(SS) is applied to the sources of the transistors 182, 186, 190 and 194. The charge pump voltage V_(CP) is applied to the gate of the transistor 186, and the voltage V_(CPD) is applied to the gate of the transistor 190. The OTA2 42 can generate enough gain for the DLL with typically less than 5 mV offset.

FIG. 6 illustrates a slave bias circuit of a DLL of the present invention. A slave bias input is a buffering circuit to buffer the slave biasing voltage for output to other delay chains for any parallel data. Thus, the voltage V_(bias slave p) is mirrored and outputted for receiving the parallel data. For instance, here there are 10 slave bias ports.

While the present invention has been described with reference to certain preferred embodiments or methods, it is to be understood that the present invention is not limited to such specific embodiments or methods. Rather, it is the inventor's contention that the invention be understood and construed in its broadest meaning as reflected by the following claims. Thus, these claims are to be understood as incorporating not only the preferred apparatuses, methods, and systems described herein, but all those other and further alterations and modifications as would be apparent to those of ordinary skilled in the art. 

We claim:
 1. A delay locked loop, comprising: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals.
 2. The delay locked loop of claim 1 wherein the charge pump comprises a first self-biased amplifier (“OTA1”), a second self-biased amplifier (“OTA2”), and transistors.
 3. The delay locked loop of claim 2 wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors, and wherein the OTA1 and the serially connected transistors are connected together to provide a dummy load for the charge pump.
 4. The delay locked loop of claim 3 wherein the source of the first transistor is connected to a first voltage, wherein the drain of the first transistor and the source of the second transistor are connected together, wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA1 are connected together, wherein the source of the third transistor is connected to the drain of the fourth transistor, wherein the source of the fourth transistor is connected to a second voltage, wherein the positive output of the OTA1 is applied to the gate of the first transistor, wherein the second voltage is applied to the gate of the second transistor, wherein the first voltage is applied to the gate of the third transistor, wherein the negative output of the OTA1 is applied to the gate of the fourth transistor, and wherein the charge pump voltage is applied to the positive input of the OTA1.
 5. The delay locked loop of claim 2 wherein the OTA2 is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.
 6. The delay locked loop of claim 5 wherein a fifth transistor and a sixth transistor of the transistors are connected in series, wherein a seventh transistor and an eighth transistor of the transistors are connected in series, wherein the sources of the fifth and seventh transistors are connected together, wherein the drains of the sixth and eighth transistors are connected together, wherein the drains of the fifth and sixth transistors and the positive input of the OTA2 are connected together, wherein the drains of the seventh and eighth transistors, the output of the OTA2, and the negative input of the OTA2 are connected together to generate the charge pump voltage, and wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.
 7. The delay locked loop of claim 6 wherein the charge pump further comprises a first switch and a second switch, wherein the positive output of the OTA1 is connected to the gate of a ninth transistor of the transistors, wherein the positive output of the OTA1 is connected to the gate of a tenth transistor of the transistors via the first switch, wherein the negative output of the OTA1 is connected to the gate of a eleventh transistor of the transistors, wherein the negative output of the OTA1 is connected to the gate of a twelfth transistor of the transistors via the second switch, wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage, wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors, wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.
 8. The delay locked loop of claim 1 further comprising an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop.
 9. The delay locked loop of claim 1 further comprising a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage.
 10. A delay locked loop, comprising: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals and wherein the charge pump comprises a first self-biased amplifier (“OTA1”), a second self-biased amplifier (“OTA2”), and transistors; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals, and wherein the OTA2 is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.
 11. The delay locked loop of claim 10 wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors, and wherein the OTA1 and the serially connected transistors are connected together to provide a dummy load for the charge pump.
 12. The delay locked loop of claim 11 wherein the source of the first transistor is connected to a first voltage, wherein the drain of the first transistor and the source of the second transistor are connected together, wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA1 are connected together, wherein the source of the third transistor is connected to the drain of the fourth transistor, wherein the source of the fourth transistor is connected to a second voltage, wherein the positive output of the OTA1 is applied to the gate of the first transistor, wherein the second voltage is applied to the gate of the second transistor, wherein the first voltage is applied to the gate of the third transistor, wherein the negative output of the OTA1 is applied to the gate of the fourth transistor, and wherein the charge pump voltage is applied to the positive input of the OTA1.
 13. The delay locked loop of claim 10 wherein a fifth transistor and a sixth transistor of the transistors are connected in series, wherein a seventh transistor and an eighth transistor of the transistors are connected in series, wherein the sources of the fifth and seventh transistors are connected together, wherein the drains of the sixth and eighth transistors are connected together, wherein the drains of the fifth and sixth transistors and the positive input of the OTA2 are connected together, wherein the drains of the seventh and eighth transistors, the output of the OTA2, and the negative input of the OTA2 are connected together to generate the charge pump voltage, and wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.
 14. The delay locked loop of claim 13 wherein the charge pump further comprises a first switch and a second switch, wherein the positive output of the OTA1 is connected to the gate of a ninth transistor of the transistors, wherein the positive output of the OTA1 is connected to the gate of a tenth transistor of the transistors via the first switch, wherein the negative output of the OTA1 is connected to the gate of a eleventh transistor of the transistors, wherein the negative output of the OTA1 is connected to the gate of a twelfth transistor of the transistors via the second switch, wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage, wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors, wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors.
 15. The delay locked loop of claim 10 further comprising an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop.
 16. The delay locked loop of claim 10 further comprising a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage.
 17. A delay locked loop, comprising: a phase detector, wherein the phase detector generates output signals as a function of a reference clock signal and a feedback clock signal; a charge pump, wherein the charge pump generates a charge pump voltage as a function of the output signals and wherein the charge pump comprises a first self-biased amplifier (“OTA1”), a second self-biased amplifier (“OTA2”), and transistors; a loop capacitor, wherein the loop capacitor is connected to the charge pump voltage to filter out noise from the charge pump voltage; an initialization circuit for providing a pulse generation signal for the charge pump voltage during initialization of the delay locked loop; a bias generation circuit, wherein the bias generation circuit generates biasing signals as a function of the charge pump voltage; and a delay chain, wherein the delay chain outputs one or more internal clock signals and the feedback clock signal as a function of the reference clock signal and the biasing signals, wherein a first transistor, a second transistor, a third transistor, and a fourth transistor of the transistors are serially connected transistors, wherein the OTA1 and the serially connected transistors are connected together to provide a dummy load for the charge pump, and wherein the OTA2 is connected in a negative feedback loop to adjust the charge pump voltage as a function of the output signals from the phase detector.
 18. The delay locked loop of claim 17 wherein the source of the first transistor is connected to a first voltage, wherein the drain of the first transistor and the source of the second transistor are connected together, wherein the drain of the second transistor, the drain of the third transistor, and the negative input of the OTA1 are connected together, wherein the source of the third transistor is connected to the drain of the fourth transistor, wherein the source of the fourth transistor is connected to a second voltage, wherein the positive output of the OTA1 is applied to the gate of the first transistor, wherein the second voltage is applied to the gate of the second transistor, wherein the first voltage is applied to the gate of the third transistor, wherein the negative output of the OTA1 is applied to the gate of the fourth transistor, and wherein the charge pump voltage is applied to the positive input of the OTA1.
 19. The delay locked loop of claim 17 wherein a fifth transistor and a sixth transistor of the transistors are connected in series, wherein a seventh transistor and an eighth transistor of the transistors are connected in series, wherein the sources of the fifth and seventh transistors are connected together, wherein the drains of the sixth and eighth transistors are connected together, wherein the drains of the fifth and sixth transistors and the positive input of the OTA2 are connected together, wherein the drains of the seventh and eighth transistors, the output of the OTA2, and the negative input of the OTA2 are connected together to generate the charge pump voltage, and wherein the gates of the fifth, sixth, seventh, and eighth transistors are controlled by the output signals of the phase detector.
 20. The delay locked loop of claim 19 wherein the charge pump further comprises a first switch and a second switch, wherein the positive output of the OTA1 is connected to the gate of a ninth transistor of the transistors, wherein the positive output of the OTA1 is connected to the gate of a tenth transistor of the transistors via the first switch, wherein the negative output of the OTA1 is connected to the gate of a eleventh transistor of the transistors, wherein the negative output of the OTA1 is connected to the gate of a twelfth transistor of the transistors via the second switch, wherein the sources of the ninth transistor and the tenth transistor are connected to a first voltage, wherein the drains of the ninth transistor and the tenth transistor are connected to the sources of the fifth and seventh transistors, wherein the sources of the eleventh transistor and the twelfth transistor are connected to a second voltage, and wherein the drains of the eleventh transistor and the twelfth transistor are connected to the sources of the sixth and eighth transistors. 